TrendForce observes that the sharp rise in reminiscence contract costs because the second half of 2025 has considerably elevated reminiscence’s share of CSP spending. Server DRAM—a key procurement class for CSPs—noticed contract costs rise by a cumulative 64% in 2H25, with an additional soar of roughly 270% anticipated in 2026. In the meantime, the same development is unfolding in NAND Flash, with enterprise SSD costs rising by round 35% in 2H25 and projected to surge by a cumulative 235% in 2026.
Some long-term agreements (LTAs) signed from 2Q26 onward have included value ceilings that would restrict additional will increase. However, HBM contract costs may nonetheless rise by 70-140% in 2027. TrendForce expects reminiscence contract costs to stay broadly elevated in 2027, persevering with to be an necessary issue driving up reminiscence’s share of CSP CapEx.
On prime of upper costs, quickly rising demand for reminiscence bits from CSPs is prompting suppliers to prioritize restricted capability for server purposes. TrendForce estimates that HBM and RDIMM mixed will account for 51% of DRAM bit provide in 2026. In 2027, course of migrations and capability ramp-ups at new fabs within the second half of the yr are anticipated to drive a 27% enhance in mixed server DRAM and HBM bit provide.
TrendForce signifies that rising reminiscence contract costs, significantly for HBM, mixed with greater bit provide, will push reminiscence’s share of CSP capex to 68% in 2027. It will have two main implications for the AI ecosystem.
First, elevated reminiscence prices present server and AI chip suppliers corresponding to NVIDIA with better justification for elevating product costs. CSPs could subsequently want to extend capital expenditures additional to take care of their focused AI chip procurement volumes. Alternatively, CSPs may extra aggressively optimize AI system reminiscence architectures by decreasing reminiscence capability per system, serving to mitigate excessive DRAM and NAND Flash prices or restricted provide allocations whereas nonetheless assembly AI chip and server cargo targets.
Such changes may take a number of varieties, together with, however not restricted to, adjusting RDIMM configurations and the quantity of HBM built-in into future AI chips, in addition to exploring AI ASICs with the mannequin structure hardwired into the silicon.
