Researchers from Google and Delft College of Expertise revealed a technical paper titled “Modern FA {Hardware} Resolution to Allow System-Degree Debug of 3D ICs.”
Summary Excerpt: “This paper presents a novel Failure Evaluation (FA) {hardware} and pattern preparation answer that permits System-Degree FA on cell System-on-a-Chip (SoC) PoP units, the place the DRAM is stacked atop the logic controller machine. The first problem in performing EFI on the underside die is offering direct line-of-sight (LoS) entry whereas preserving the highest DRAM performance via extraordinarily small interconnects known as By means of Interposer Vias (TIVs). For the primary time, this groundbreaking {hardware} answer overcomes the problem of connecting a DRAM atop the SoC silicon, using the smallest attainable interposer pin pitch (∼210 um) and superior DRAM card design that comes with stringent design guidelines to allow as much as 6.3 Gbps utilizing a DDR coaching take a look at and runs customary Android stress purposes. ”
Discover the technical paper here. 2026.
Endrinal, Lesly, Jehan Saujauddin, YuanChung Ho, Dilbagh Singh, Sasi Sekaran Sundaresan, Vinod Kumar Kakumanu, Jessen Gonzalez, Willem D. van Driel, and G. Q. Zhang. “Modern FA {hardware} answer to allow system-level debug of 3D ICs.” Microelectronics Reliability 184 (2026): 116230. Artistic Commons license.
